1. Field of the Invention
The present invention is related to a method of adjusting a signal delay time of a circuit system, and more particularly, to a method of dynamically adjusting a signal delay time of a circuit system according to the operational environment of the circuit system.
2. Description of the Prior Art
Generally speaking, an electronic device coordinates different components of the electronic device by using the same clock. For example, in an electronic device with a Dynamic random access memory (DRAM), the output signals of the DRAM are adjusted to be consistent with the system clock of the electronic device. Therefore, the DRAM and the rest components of the electronic device are all controlled by the system clock so as to operate synchronously with each other. However, electronic devices generally have a clock skew problem. The clock skew problem means the clock reaches different components of an electronic device at different times, which is often caused by the delay of the clock buffer circuit and the driving circuit, or the delay of the other resistor-inductor circuit. Thus, the above-mentioned DRAM can not be synchronized with the system clock because of the clock skew problem, causing an abnormal operation of the DRAM.
Please refer to FIG. 1. FIG. 1 is a waveform diagram of output data of a conventional Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The timing of outputting data signals is enabled to be on active duty by the rising or falling edge of the clock signals CK or CKB. The phase of the clock signal CK is opposite to the clock signal CKB. DQ0˜DQ7 are the data signals transmitted by the data buses. Since the transmitting paths of the data signals are different, the phases of the data signals are different. That is, the start of the available interval of the data signal DQ7 is the earliest one, and that of the data signal DQ0 is the latest one. By contrast, the end of the available interval of the data signal DQ7 is also the earliest one, and that of the data signal DQ0 is the latest one. In FIG. 1, a data strobe signal DQS is designed as a sampling reference signal of the data signal, tHP is the half cycle of the clock signal CK, tDQS is the interval between the positive edge or the negative edge of the data strobe signal DQS to the start of the available interval of the data signal DQ0, tQH is the interval between the positive edge or the negative edge of the data strobe signal DQS to the end of the available interval of the data signal DQ7, and the overlap between the available intervals of the data signals DQ0˜DQ7 is a data valid window DVW.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating a conventional delay circuit 20. The delay circuit 20 is utilized for generating a signal delay time according to a delay value of the delay chain. Furthermore, for the sake of accuracy and stability on data access, the positive edge or the negative edge of the data strobe signal DQS is preferably postponed to the center of the data valid window, and therefore a delay circuit 20 capable of adjusting the signal delay time is put forth to satisfy the aforesaid preferable requirement. As shown in FIG. 2, the delay circuit 20 selects one of the delay chains 2124 as the best delay path through a multiplexer 26 enabled to be on active duty by a tester 25 during the testing stage of an electronic device. After the delay interval between the input terminal and output terminal is tuned to a default value, the signal delay time is constant, not variable. However, several disadvantages exist in the conventional method of adjusting the signal delay time and are to be overcome. For example, the best delay path of an electronic device has to be determined before the electronic device with the delay chain circuit is used. Therefore, the signal delay time can not be dynamically adjusted according to the actual operational environment of the electronic device. For example, the signal delay time can not be dynamically adjusted when the electronic device operates at a rising temperature or at a higher speed. In addition, each component of the electronic device has to predetermine their delay paths during the test phase, increasing the cost and the time of manufacturing and testing.
For example, the data valid window of a PC 133 DDR SDRAM module requires a minimum interval not less than 2.625 nanoseconds (ns). Considering the skew time caused by the various characteristics of the printed circuit board (around 0.513 ns) during the minimum data valid window, the setup and hold time of the controller (around 0.6 ns), and the strobe placement uncertainty of the data strobe signal DQS (around 0.4 ns), the residual margin time is only 0.1 ns. Because the strobe placement uncertainty of the data strobe DQS can be doubled when surrounding temperature varies from case to case, errors occur frequently in data access.
In conclusion, a method of dynamically adjusting the signal delay time of the circuit system according to the operational environment is required for accuracy and stability on data access.